The present invention generally relates to semiconductor memory devices and more particularly to a fabrication process of a dynamic random access memory (DRAM) that stores information in a capacitor in the form of electric charges.
In semiconductor memory devices that store information in the form of electric charges such as a DRAM, it is generally practiced to employ a multiple-well structure in which a memory cell is provided in a first well of a first conductivity type formed in a second well of a second, different conductivity type. By employing such a multiple-well structure, it is possible to absorb unwanted positive and negative electric charges, which are created upon incidence of alpha particles into the semiconductor substrate, by the wells of the respective conductivity types. Thereby, the problem of destruction of information stored in the memory device by such charged particles is substantially reduced. Yoshikawa et al, Dig. Tech, Papers, Symp. VLSI Technology 1989, pp.67-68 describes such a DRAM that uses the multiple-well construction for the peripheral circuits of the DRAM.
Meanwhile, there has been a problem in the conventional fabrication process of DRAMs having a large integration density, in that the height of the memory cell capacitor has to be increased relatively with respect to the lateral size thereof, in order to compensate for the decrease of capacitance caused as a result of miniaturization of the device. When the height of the memory cell capacitor is increased as such, on the other hand, the height or level of the chip surface for the region on which a memory cell array is formed, increases as compared with the region on which a peripheral circuit such as sense amplifier is formed. In other words, there appears a step at the boundary between the memory cell array region and the peripheral circuit region on a common semiconductor chip.
It should be noted that high resolution optical exposure systems, used for exposing integrated circuits of very large integration density, generally uses a high resolution optical system having a large numerical aperture. As an optical system having a large numerical aperture has an extremely limited focal depth, it will be noted that existence of such a step on the chip causes a substantial difficulty in exposing a conductor pattern extending continuously from the memory cell array region to the peripheral circuit region.
In order to avoid this problem, it is proposed to minimize the step height on the chip by lowering the level of the memory cell array region with respect to other regions of the chip. For example, Sagara, K., et al., Dig. Tech. Papers, Symp. VLSI Technology, 1992, pp.10-11 describes a process in which the memory cell array region is first oxidized to form an oxide film of substantial thickness, followed by an etching process for selectively removing the oxide film thus formed. According to the process of the foregoing reference, it will be noted that there is formed a recess structure on the semiconductor chip in correspondence to the memory cell array region.
FIGS. 1A-1D show a conventional process of fabricating a semiconductor memory device having such a recess structure on a silicon substrate including the process for forming a multiple well structure in correspondence to the memory cell array region and a twin well structure in correspondence to the peripheral circuit region, wherein the twin well structure is a structure in which a p-type well and an n-type well are formed adjacent with each other side by side in a silicon substrate.
Referring to FIG. 1A, a thin silicon oxide film 12 is formed on a surface of a p-type silicon substrate 11 by means of a thermal oxidation process conducted in a dry oxygen environment. Further, the silicon oxide film 12 is subjected to a spin coating process of photo resist to form a resist layer not illustrated, followed by a photolithographic patterning process of the resist layer to form a resist pattern 13. Further, an ion implantation process of n-type dopant such as As or P is conducted into the substrate 11 through the oxide film 12 while using the resist pattern 13 as a mask. After removing the mask 13, an annealing process is conducted for causing a diffusion of the dopants. As a result, n-type wells 11a and 11b are formed as indicated in FIG. 1A. In FIG. 1A, it should be noted that the well 11a corresponds to the peripheral circuit, while the well 11b corresponds to the memory cell array region.
Next, in a step of FIG. 1B, a new resist pattern 14 is formed on the structure of FIG. 1A by a spin coating process, followed by a photolithographic patterning process similarly as before. Further, by conducting an ion implantation of p-type dopants such as B into the substrate while using the pattern 14 as a mask, it is possible to form a p-type well 11c such that the well 11c is located adjacent to the well 11a. Further, another p-type well 11d is formed inside the n-type well 11b in the memory cell array region as indicated in FIG. 1B.
Next, in a step of FIG. 1C, the resist pattern 14 is removed, and an annealing process is conducted for causing the diffusion of the dopants. Next, a SiN layer and a resist layer are deposited successively upon the silicon oxide film 12 covering the surface of the substrate 11, and a photolithographic patterning process is applied to the SiN layer to form a SiN pattern 15. After the SiN pattern 15 is formed, the resist pattern used for the patterning of the SiN layer is removed, and a thermal oxidation process is conducted in a wet oxygen environment to form a thick oxide film 16 in correspondence to the part of the substrate not protected by the SiN mask 15 as indicated in FIG. 1C.
Next, the silicon oxide film 16 is removed by an etching process and a structure of FIG. 1D is obtained. In FIG. 1D, it will be noted that there is formed a recess structure in the well 11d in correspondence to the memory cell array region. Further, a memory cell capacitor MC and an insulation layer 19 covering the memory cell capacitor MC are formed on the p-type well 11d as indicated in FIG. 1E, and a contact hole 19a is formed in the insulation layer 19. By providing an electrode 20 such that the electrode 20 fills the contact hole 19a, it is possible to bias the well 11d at a desired level.
In the conventional process of FIGS. 1A-1D, it will be noted that three mask processes are required as indicated in FIGS. 1A, 1B and 1C, wherein each masking process includes various processes such as deposition of SiN and resist layers, patterning of the resist layer by a photolithographic process, patterning of the SiN layer by using a resist mask, removal of the resist mask and the SiN mask, and so on. Thus, the process of FIGS.1A-1D is expensive for fabricating a DRAM.
Further, the conventional process described before has another drawback in that it is necessary to provide the contact hole 19a thorough the thick oxide film 16, while the exposure of such a deep contact hole by a high resolution optical system inevitably raises a problem of limited focal depth. In addition, the process to fill such the contact hole 19 having a large aspect ratio by the electrode 20 tends to cause a problem of poor step coverage.